Modified ATPG method by feeling don’t care bit for reduction of switching activities
نویسنده
چکیده
Test power is major issue of current scenario of VLSI testing. There are different test pattern generation techniques for testing of combinational circuits. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bit of the test vector to optimize the switching activities. Finally this concept produces low power testing.
منابع مشابه
Low Power testing by don’t care bit filling technique
Test power is major issue of recent scenario of VLSI testing. There are many test pattern generation techniques for testing of combinational circuits with different tradeoffs. The don’t care bit filling method can be used for effective test data compression as well as reduction in scan power. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bi...
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تاریخ انتشار 2011